/*
 * Mediatek's MT6753 SoC device tree source
 *
 * Copyright (c) 2013 MediaTek Co., Ltd.
 *              http://www.mediatek.com
 *
 */

/ {
	model = "MT6753";
	compatible = "mediatek,MT6735";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	/* chosen */
	chosen {
               bootargs = "console=tty0 console=ttyMT0,921600n1 root=/dev/ram initrd=0x44000000,0x300000 loglevel=8 androidboot.hardware=mt6735";
	};

    /* Do not put any bus before mtk-msdc, because it should be mtk-msdc.0 for partition device node usage */
  mtk-msdc {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0 0 0xffffffff>;

		MSDC0@0x11230000 {
			compatible = "mediatek,MSDC0";
			reg = <0x11230000 0x10000  /* MSDC0_BASE   */
			       0x10000E84 0x2>;    /* FPGA PWR_GPIO, PWR_GPIO_EO */
			interrupts = <0 79 0x8>;
		};

		MSDC1@0x11240000 {
			compatible = "mediatek,MSDC1";
			reg = <0x11240000 0x10000  /* MSDC1_BASE   */
			       0x10000E84 0x2>;    /* FPGA PWR_GPIO, PWR_GPIO_EO */
			interrupts = <0 80 0x8>;
		};

		MSDC2@0x11250000 {
			compatible = "mediatek,MSDC2";
			reg = <0x11250000 0x10000  /* MSDC2_BASE   */
			       0x10000E84 0x2>;    /* FPGA PWR_GPIO, PWR_GPIO_EO */
			interrupts = <0 81 0x8>;
		};

		MSDC3@0x11260000 {
			compatible = "mediatek,MSDC3";
			reg = <0x11260000 0x10000  /* MSDC3_BASE   */
			       0x10000E84 0x2>;    /* FPGA PWR_GPIO, PWR_GPIO_EO */
			interrupts = <0 82 0x8>;
		};
  };


	cpus {	#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x000>;
			enable-method = "mt-boot";
			cpu-release-addr = <0x0 0x40000200>;
			clock-frequency = <1300000000>;
		};


		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x001>;
			enable-method = "mt-boot";
			cpu-release-addr = <0x0 0x40000200>;
			clock-frequency = <1300000000>;
		};

		cpu2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x002>;
			enable-method = "mt-boot";
			cpu-release-addr = <0x0 0x40000200>;
			clock-frequency = <1300000000>;
		};

		cpu3: cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x003>;
			enable-method = "mt-boot";
			cpu-release-addr = <0x0 0x40000200>;
			clock-frequency = <1300000000>;
		};

		cpu4: cpu@4 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x100>;
			enable-method = "mt-boot";
			cpu-release-addr = <0x0 0x40000200>;
			clock-frequency = <2000000000>;
		};

		cpu5: cpu@5 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x101>;
			enable-method = "mt-boot";
			cpu-release-addr = <0x0 0x40000200>;
			clock-frequency = <2000000000>;
		};

		cpu6: cpu@6 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x102>;
			enable-method = "mt-boot";
			cpu-release-addr = <0x0 0x40000200>;
			clock-frequency = <2000000000>;
		};

		cpu7: cpu@7 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x103>;
			enable-method = "mt-boot";
			cpu-release-addr = <0x0 0x40000200>;
			clock-frequency = <2000000000>;

		};

	};

	memory@00000000 {
		device_type = "memory";
		reg = <0 0x40000000 0 0x40000000>;
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		/* reserve 192KB at DRAM start + 48MB */
		ATF-reserved-memory {
			compatible = "ATF-reserved-memory";
			no-map;
			reg = <0 0x43000000 0 0x30000>;
		};

		reserve-memory-ccci_md1 {
			compatible = "reserve-memory-ccci_md1";
			no-map;
			size = <0 0x3810000>; // md_size+smem_size
			alignment = <0 0x2000000>;
			alloc-ranges = <0 0x40000000 0 0xC0000000>;
		};

		consys-reserve-memory {
			compatible = "consys-reserve-memory";
			no-map;
			size = <0 0x200000>;
			alignment = <0 0x200000>;
		};

		/*
		reserve-memory-test {
			compatible = "reserve-memory-test";
			no-map;
			size = <0 0x4000000>;
			alignment = <0 0x2000000>;
		};

		mrdump-reserved-memory {
			compatible = "mrdump";
			reg = <0 0x80000000 0 0x4000000>;
		};
		*/
	};

	gic: interrupt-controller@0x10220000 {
		compatible = "mtk,mt-gic";
		#interrupt-cells = <3>;
		#address-cells = <0>;
		interrupt-controller;
		reg = <0 0x10221000 0 0x1000>,
		      <0 0x10222000 0 0x1000>,
		      <0 0x10200620 0 0x1000>;
		interrupts = <1 9 0xf04>;

		gic-cpuif@0 {
			compatible = "arm,gic-cpuif";
			cpuif-id = <0>;
			cpu = <&cpu0>;
		};

		gic-cpuif@1 {
			compatible = "arm,gic-cpuif";
			cpuif-id = <1>;
			cpu = <&cpu1>;
		};

		gic-cpuif@2 {
			compatible = "arm,gic-cpuif";
			cpuif-id = <2>;
			cpu = <&cpu2>;
		};

		gic-cpuif@3 {
			compatible = "arm,gic-cpuif";
			cpuif-id = <3>;
			cpu = <&cpu3>;
		};
		
		gic-cpuif@4 {
			compatible = "arm,gic-cpuif";
			cpuif-id = <4>;
			cpu = <&cpu4>;
		};
		
		gic-cpuif@5 {
			compatible = "arm,gic-cpuif";
			cpuif-id = <5>;
			cpu = <&cpu5>;
		};
		
		gic-cpuif@6 {
			compatible = "arm,gic-cpuif";
			cpuif-id = <6>;
			cpu = <&cpu6>;
		};
		
		gic-cpuif@7 {
			compatible = "arm,gic-cpuif";
			cpuif-id = <7>;
			cpu = <&cpu7>;
		};		

	};

	CPUXGPT@0x10200000 {
		compatible = "mediatek,CPUXGPT";
		reg = <0 0x10200000 0 0x1000>;
		interrupts = <0 64 0x4>,
			           <0 65 0x4>,
			           <0 66 0x4>,
			           <0 67 0x4>,
			           <0 68 0x4>,
			           <0 69 0x4>,
			           <0 70 0x4>,
			           <0 71 0x4>;
	};

	APXGPT@0x10004000 {
		compatible = "mediatek,APXGPT";
		reg = <0 0x10004000 0 0x1000>;
		interrupts = <0 152 0x8>;
		clock-frequency = <13000000>;
	};

	timer {
    compatible = "arm,armv8-timer";
    interrupts = <1 13 0x8>, /*Secure Physical Timer Event*/
                 <1 14 0x8>, /*Non-Secure Physical Timer Event*/
                 <1 11 0x8>, /*Virtual Timer Event*/
                 <1 10 0x8>; /*Hypervisor Timer Event*/
    clock-frequency = <13000000>;
  };

	bus {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0 0 0xffffffff>;

		INFRACFG_AO@0x10000000 {
			compatible = "mediatek,INFRACFG_AO";
			reg = <0x10000000 0x1000>;
		};

		PWRAP@0x10001000 {
			compatible = "mediatek,PWRAP";
			reg = <0x10001000 0x1000>;
			interrupts = <0 163 0x4>;
		};

		PERICFG@0x10002000 {
			compatible = "mediatek,PERICFG";
			reg = <0x10002000 0x1000>;
		};

    FHCTL@0x10209F00 {
			compatible = "mediatek,FHCTL";
			reg = <0x10209F00 0x100>;
		};

		KP@0x10003000 {
			compatible = "mediatek,KP";
			reg = <0x10003000 0x1000>;
			interrupts = <0 164 0x2>;
		};

		eintc: EINTC@0x10005000 {
			compatible = "mtk,mt-eic";
			reg = <0x10005000 0x1000>;
			interrupts = <0 153 0x4>;

			#interrupt-cells = <2>;
			interrupt-controller;

			max_eint_num = <213>;
			mapping_table_entry = <0>;
		};

		SLEEP@0x10006000 {
			compatible = "mediatek,SLEEP";
			reg = <0x10006000 0x1000>;
			interrupts = <0 165 0x8>,
			             <0 166 0x8>,
			             <0 167 0x8>,
			             <0 168 0x8>;
		};

		DEVAPC_AO@0x10007000 {
			compatible = "mediatek,DEVAPC_AO";
			reg = <0x10007000 0x1000>;
		};

		SEJ@0x10008000 {
			compatible = "mediatek,SEJ";
			reg = <0x10008000 0x1000>;
			interrupts = <0 174 0x8>;
		};

		RSVD@0x10009000 {
			compatible = "mediatek,RSVD";
			reg = <0x10009000 0x1000>;
		};

        BAT_METTER {
            compatible = "mediatek,bat_meter";
        };

        BAT_NOTIFY {
            compatible = "mediatek,bat_notify";
        };

		BATTERY {
			compatible = "mediatek,battery";
		};

		MDCLDMA@0x1000A000 {
			compatible = "mediatek,MDCLDMA";
			reg = <0x1000A000 0x1000>, /*AP_CLDMA_AO*/
						<0x1000B000 0x1000>, /*MD_CLDMA_AO*/
						<0x1021A000 0x1000>, /*AP_CLDMA_PDN*/
						<0x1021B000 0x1000>, /*MD_CLDMA_PDN*/
						<0x1020A000 0x1000>, /*AP_CCIF_BASE*/
						<0x1020B000 0x1000>; /*MD_CCIF_BASE*/
			cell-index = <0>;
			interrupts = <0 145 0x4>, /*IRQ_CLDMA*/
				     <0 140 0x8>, /*IRQ_CCIF*/
				     <0 223 0x2>; /*IRQ_MDWDT*/
			cldma,major = <184>;
			cldma,minor_base = <0>;
			cldma,capability = <2>;
			md_smem_size = <0x10000>; //md share memory size
		};

		MDC2K@0 {
			compatible = "mediatek,MDC2K";
			reg = <0x3a00b01c 0x10>, // C2K CHIP ID
				  <0x1021C800 0x300>, // MD1 PCCIF
				  <0x1021D800 0x300>, // MD3 PCCIF
				  <0x39017000 0x1000>, // C2K IRAM
				  <0x39003300 0x200>, // C2K IRAM part 2
				  <0x3900BA80 0x200>; // C2K IRAM part 3
			interrupts = <0 221 0x2>; // WDT
		};

		DBGAPB_BASE@0x1011A000{
			compatible = "mediatek,DBGAPB_BASE";
			reg = <0x1011A000 0x100>;// MD debug register
		};

		MCUCFG@0x10200000 {
			compatible = "mediatek,MCUCFG";
			reg = <0x10200000 0x200>;
			interrupts = <0 71 0x4>;
		};

		RESERVED@0x10200200 {
			compatible = "mediatek,RESERVED";
			reg = <0x10200200 0x200>;
		};

		MCUSYS_MISCCFG@0x10200400 {
			compatible = "mediatek,MCUSYS_MISCCFG";
			reg = <0x10200400 0x200>;
		};

		MCUSYS_MCUCFG@0x10200600 {
			compatible = "mediatek,MCUSYS_MCUCFG";
			reg = <0x10200600 0xa00>;
		};

		INFRACFG@0x10201000 {
			compatible = "mediatek,INFRACFG";
			reg = <0x10201000 0x1000>;
		};

		SRAMROM@0x10202000 {
			compatible = "mediatek,SRAMROM";
			reg = <0x10202000 0x1000>;
		};

		EMI@0x10203000 {
			compatible = "mediatek,EMI";
			reg = <0x10203000 0x1000>;
			interrupts = <0 136 0x4>;
		};

		SYS_CIRQ@0x10204000 {
			compatible = "mediatek,SYS_CIRQ";
			reg = <0x10204000 0x1000>;
			interrupts = <0 231 0x8>;
			cirq_num = <159>;
			spi_start_offset = <72>;
		};

		M4U@0x10205000 {
                        cell-index = <0>;
			compatible = "mediatek,M4U";
			reg = <0x10205000 0x1000>;
			interrupts = <0 146 0x8>;
		};

		EFUSEC@0x10206000 {
			compatible = "mediatek,EFUSEC";
			reg = <0x10206000 0x1000>;
		};

		DEVAPC@0x10207000 {
			compatible = "mediatek,DEVAPC";
			reg = <0x10207000 0x1000>;
			interrupts = <0 134 0x8>;
		};

		BUS_DBG@0x10208000 {
			compatible = "mediatek,BUS_DBG";
			reg = <0x10208000 0x1000>;
			interrupts = <0 137 0x8>;
		};

		APMIXED@0x10209000 {
			compatible = "mediatek,APMIXED";
			reg = <0x10209000 0x1000>;
		};


		RSVD@0x1020C000 {
			compatible = "mediatek,RSVD";
			reg = <0x1020C000 0x1000>;
		};

		INFRA_MBIST@0x1020D000 {
			compatible = "mediatek,INFRA_MBIST";
			reg = <0x1020D000 0x1000>;
		};

		DRAMC_NAO@0x1020E000 {
			compatible = "mediatek,DRAMC_NAO";
			reg = <0x1020E000 0x1000>;
		};

		TRNG@0x1020F000 {
			compatible = "mediatek,TRNG";
			reg = <0x1020F000 0x1000>;
			interrupts = <0 141 0x8>;
		};

		CKSYS@0x10210000 {
			compatible = "mediatek,CKSYS";
			reg = <0x10210000 0x1000>;
		};

		GPIO@0x10211000 {
			compatible = "mediatek,GPIO";
			reg = <0x10211000 0x1000>;
		};

		TOPRGU@0x10212000 {
			compatible = "mediatek,TOPRGU";
			reg = <0x10212000 0x1000>;
			interrupts = <0 128 0x2>;
		};

		DDRPHY@0x10213000 {
			compatible = "mediatek,DDRPHY";
			reg = <0x10213000 0x1000>;
		};

		DRAMC0@0x10214000 {
			compatible = "mediatek,DRAMC0";
			reg = <0x10214000 0x1000>;
		};

		MIPI_RX_ANA_CSI0@0x10215000 {
			compatible = "mediatek,MIPI_RX_ANA_CSI0";
			reg = <0x10215000 0x1000>;
		};

 		CCI400@0x10390000 {
			compatible = "mediatek,CCI400";
			reg = <0x10390000 0x10000>;
		};

		GCPU@0x10216000 {
			compatible = "mediatek,GCPU";
			reg = <0x10216000 0x1000>;
			interrupts = <0 150 0x8>;
		};

		GCE@0x10217000 {
			compatible = "mediatek,GCE";
			reg = <0x10217000 0x1000>;
			interrupts = <0 151 0x8>,
			             <0 148 0x8>;
		};

		CQDMA@0x10217C00 {
			compatible = "mediatek,CQDMA";
			reg = <0x10217C00 0xC00>;
			interrupts = <0 143 0x8>;
			nr_channel = <1>;
		};

		AP_CCIF1@0x10218000 {
			compatible = "mediatek,AP_CCIF1";
			reg = <0x10218000 0x1000>;
			interrupts = <0 139 0x4>;
		};

		MD_CCIF1@0x10219000 {
			compatible = "mediatek,MD_CCIF1";
			reg = <0x10219000 0x1000>;
		};

		MD2MD_CCIF0@0x1021C000 {
			compatible = "mediatek,MD2MD_CCIF0";
			reg = <0x1021C000 0x1000>;
		};

		MD2MD_CCIF1@0x1021D000 {
			compatible = "mediatek,MD2MD_CCIF1";
			reg = <0x1021D000 0x1000>;
		};

		MDSYS_INTF@0x1021E000 {
			compatible = "mediatek,MDSYS_INTF";
			reg = <0x1021E000 0x1000>;
		};

		DBGAPB@0x10400000 {
			compatible = "mediatek,DBGAPB";
			reg = <0x10400000 0xc>;
			interrupts = <0 132 0x8>;
		};

		DEBUGTOP_CA7L@0x10800000 {
			compatible = "mediatek,DEBUGTOP_CA7L";
			reg = <0x10800000 0x4>;
		};

		DEBUGTOP_MD1@0x10450000 {
			compatible = "mediatek,DEBUGTOP_MD1";
			reg = <0x10450000 0x20000>;
		};

		DEBUGTOP_MD2@0x10470000 {
			compatible = "mediatek,DEBUGTOP_MD2";
			reg = <0x10470000 0x10000>;
		};

		CA9@0x10220000 {
			compatible = "mediatek,CA9";
			reg = <0x10220000 0x8000>;
		};

		MCU_BIU@0x10300000 {
			compatible = "mediatek,MCU_BIU";
			reg = <0x10300000 0x8000>;
		};

		CPU_DBGAPB {
			compatible = "mediatek,DBG_DEBUG";
			num = <8>;
			reg =  <0x10810000 0x1000
				0x10910000 0x1000
				0x10A10000 0x1000
				0x10B10000 0x1000
				0x10C10000 0x1000
				0x10D10000 0x1000
				0x10E10000 0x1000
				0x10F10000 0x1000>;
		};

		AP_DMA@0x11000000 {
			compatible = "mediatek,AP_DMA";
			reg = <0x11000000 0x1000>;
			interrupts = <0 114 0x8>;
		};

		AP_DMA_IRDA@0x11000100 {
			compatible = "mediatek,AP_DMA_IRDA";
			reg = <0x11000100 0x80>;
			interrupts = <0 98 0x8>;
		};


		AP_DMA_UART0_TX@0x11000400 {
			compatible = "mediatek,AP_DMA_UART0_TX";
			reg = <0x11000400 0x80>;
			interrupts = <0 103 0x8>;
		};

		AP_DMA_UART0_RX@0x11000480 {
			compatible = "mediatek,AP_DMA_UART0_RX";
			reg = <0x11000480 0x80>;
			interrupts = <0 104 0x8>;
		};

		AP_DMA_UART1_TX@0x11000500 {
			compatible = "mediatek,AP_DMA_UART1_TX";
			reg = <0x11000500 0x80>;
			interrupts = <0 105 0x8>;
		};

		AP_DMA_UART1_RX@0x11000580 {
			compatible = "mediatek,AP_DMA_UART1_RX";
			reg = <0x11000580 0x80>;
			interrupts = <0 106 0x8>;
		};

		AP_DMA_UART2_TX@0x11000600 {
			compatible = "mediatek,AP_DMA_UART2_TX";
			reg = <0x11000600 0x80>;
			interrupts = <0 107 0x8>;
		};

		AP_DMA_UART2_RX@0x11000680 {
			compatible = "mediatek,AP_DMA_UART2_RX";
			reg = <0x11000680 0x80>;
			interrupts = <0 108 0x8>;
		};

		AP_DMA_UART3_TX@0x11000700 {
			compatible = "mediatek,AP_DMA_UART3_TX";
			reg = <0x11000700 0x80>;
			interrupts = <0 109 0x8>;
		};

		AP_DMA_UART3_RX@0x11000780 {
			compatible = "mediatek,AP_DMA_UART3_RX";
			reg = <0x11000780 0x80>;
			interrupts = <0 110 0x8>;
		};

		AP_DMA_UART4_TX@0x11000800 {
			compatible = "mediatek,AP_DMA_UART4_TX";
			reg = <0x11000800 0x80>;
			interrupts = <0 111 0x8>;
		};

		AP_DMA_UART4_RX@0x11000880 {
			compatible = "mediatek,AP_DMA_UART4_RX";
			reg = <0x11000880 0x80>;
			interrupts = <0 112 0x8>;
		};

		AUXADC@0x11001000 {
			compatible = "mediatek,AUXADC";
			reg = <0x11001000 0x1000>;
			interrupts = <0 76 0x2>;
		};

		AP_UART0@0x11002000 {
                        cell-index = <0>;
			compatible = "mediatek,AP_UART0";
			reg = <0x11002000 0x1000>;
			interrupts = <0 91 0x8>;
		};

		AP_UART1@0x11003000 {
                        cell-index = <1>;
			compatible = "mediatek,AP_UART1";
			reg = <0x11003000 0x1000>;
			interrupts = <0 92 0x8>;
		};

		AP_UART2@0x11004000 {
                        cell-index = <2>;
			compatible = "mediatek,AP_UART2";
			reg = <0x11004000 0x1000>;
			interrupts = <0 93 0x8>;
		};

		AP_UART3@0x11005000 {
                        cell-index = <3>;
			compatible = "mediatek,AP_UART3";
			reg = <0x11005000 0x1000>;
			interrupts = <0 94 0x8>;
		};

		AP_UART4@0x1100D000 {
                        cell-index = <4>;
			compatible = "mediatek,AP_UART4";
			reg = <0x1100D000 0x1000>;
			interrupts = <0 95 0x8>;
		};

		PWM@0x11006000 {
			compatible = "mediatek,PWM";
			reg = <0x11006000 0x1000>;
			interrupts = <0 77 0x8>;
		};

		I2C0@0x11007000 {
			compatible = "mediatek,I2C0";
			cell-index = <0>;
			reg = <0x11007000 0x1000>;
			interrupts = <0 84 0x8>,
			             <0 98 0x8>;
		};

		I2C1@0x11008000 {
			compatible = "mediatek,I2C1";
			cell-index = <1>;
			reg = <0x11008000 0x1000>;
			interrupts = <0 85 0x8>,
			             <0 99 0x8>;
		};

		I2C2@0x11009000 {
			compatible = "mediatek,I2C2";
			cell-index = <2>;
			reg = <0x11009000 0x1000>;
			interrupts = <0 86 0x8>,
			             <0 100 0x8>;
		};

	  I2C3@0x1100F000 {
			compatible = "mediatek,I2C3";
			cell-index = <3>;
			reg = <0x1100F000 0x1000>;
			interrupts = <0 87 0x8>,
			             <0 101 0x8>;
		};

    I2C4@0x11012000 {
			compatible = "mediatek,I2C4";
			cell-index = <4>;
			reg = <0x11012000 0x1000>;
			interrupts = <0 88 0x8>,
			             <0 102 0x8>;
		};

		SPI1@0x1100A000 {
			cell-index = <0>;
			spi-padmacro = <0>;
			compatible = "mediatek,SPI1";
			reg = <0x1100A000 0x1000>;
			interrupts = <0 118 0x8>;
		};

		THERM_CTRL@0x1100B000 {
			compatible = "mediatek,THERM_CTRL";
			reg = <0x1100B000 0x1000>;
			interrupts = <0 78 0x8>;
		};

		PTP_FSM@0x1100B000 {
			compatible = "mediatek,PTP_FSM";
			reg = <0x1100B000 0x1000>;
			interrupts = <0 125 0x8>;
		};

		AP_DMA_BTIF_TX@0x11000900 {
			compatible = "mediatek,AP_DMA_BTIF_TX";
			reg = <0x11000900 0x80>;
			interrupts = <0 113 0x8>;
		};

		AP_DMA_BTIF_RX@0x11000980 {
			compatible = "mediatek,AP_DMA_BTIF_RX";
			reg = <0x11000980 0x80>;
			interrupts = <0 114 0x8>;
		};

		BTIF@0x1100C000 {
			compatible = "mediatek,BTIF";
			reg = <0x1100C000 0x1000>;
			interrupts = <0 90 0x8>;
		};

    CONSYS@0x18070000 {
        compatible = "mediatek,CONSYS";
        reg = <0x18070000 0x0200>,  /*CONN_MCU_CONFIG_BASE      */
              <0x10212000 0x0100>,  /*AP_RGU_BASE               */
              <0x10000000 0x2000>,  /*TOPCKGEN_BASE             */
              <0x10006000 0x1000>;  /*SPM_BASE                  */
	    interrupts = <0 229 0x8>, /*BGF_EINT                  */
	                 <0 227 0x8>; /*WDT_EINT                  */
    };
		mt3326-gps@0xffffffff {
			compatible = "mediatek,mt3326-gps";
		};
		BTCVSD@0x18000000 {
			compatible = "mediatek,audio_bt_cvsd";
			reg = <0x18000000 0x1000>, /*CVSD REG_BASE*/
			      <0x18080000 0x1000>; /*CVSD SRAM*/
			interrupts = <0 230 0x8>;
		};

		WIFI@0x180F0000 {
			compatible = "mediatek,WIFI";
			reg = <0x180F0000 0x005c>;
			interrupts = <0 228 0x8>;
		};

		NFI@0x1100D000 {
			compatible = "mediatek,NFI";
			reg = <0x1100D000 0x1000>;
		};

		NFI_ECC@0x1100E000 {
			compatible = "mediatek,NFI_ECC";
			reg = <0x1100E000 0x1000>;
		};

		DISP_PWM0@0x1100E000 {
			compatible = "mediatek,DISP_PWM0";
			reg = <0x1100E000 0x1000>;
		};

		IRDA@0x11010000 {
			compatible = "mediatek,IRDA";
			reg = <0x11010000 0x1000>;
			interrupts = <0 123 0x4>;
		};

		IRTX@0x11011000 {
			compatible = "mediatek,IRTX";
			reg = <0x11011000 0x1000>;
			interrupts = <0 124 0x4>;
			major = <100>;
			pwm_ch = <0>;
		};

		USB0@0x11200000 {
			compatible = "mediatek,USB0";
			cell-index = <0>;
			reg = <0x11200000 0x10000>,
			      <0x11210000 0x10000>;
			interrupts = <0 72 0x8>;
			mode = <2>;
			multipoint = <1>;
			dyn_fifo = <1>;
			soft_con = <1>;
			dma = <1>;
			num_eps = <16>;
			dma_channels = <8>;
		};

		AUDIO@0x11220000 {
			compatible = "mediatek,AUDIO";
			reg = <0x11220000 0x10000>;
			interrupts = <0 144 0x8>;
		};
		MT_SOC_DL1_PCM@0x11220000 {
			compatible = "mediatek,mt_soc_pcm_dl1";
			reg = <0x11220000 0x1000>;
			interrupts = <0 144 0x8>;
			audclk-gpio = <143 0>;
			audmiso-gpio = <144 0>;
			audmosi-gpio = <145 0>;
			vowclk-gpio = <148 0>;
			extspkamp-gpio = <117 0>;
			i2s1clk-gpio = <80 0>;
			i2s1dat-gpio = <78 0>;
			i2s1mclk-gpio = <9 0>;
			i2s1ws-gpio = <79 0>;
		};

		MT_SOC_UL1_PCM@0x11220000 {
			compatible = "mediatek,mt_soc_pcm_capture";
		};

		MT_SOC_VOICE_MD1@0x11220000 {
			compatible = "mediatek,mt_soc_pcm_voice_md1";
		};

		MT_SOC_HDMI_PCM@0x11220000 {
			compatible = "mediatek,mt_soc_pcm_hdmi";
		};

		MT_SOC_ULDLLOOPBACK_PCM@0x11220000 {
			compatible = "mediatek,mt_soc_pcm_uldlloopback";
		};

		MT_SOC_I2S0_PCM@0x11220000 {
			compatible = "mediatek,mt_soc_pcm_dl1_i2s0";
		};

		MT_SOC_MRGRX_PCM@0x11220000 {
			compatible = "mediatek,mt_soc_pcm_mrgrx";
		};

		MT_SOC_MRGRX_AWB_PCM@0x11220000 {
			compatible = "mediatek,mt_soc_pcm_mrgrx_awb";
		};

		MT_SOC_FM_I2S_PCM@0x11220000 {
			compatible = "mediatek,mt_soc_pcm_fm_i2s";
		};

		MT_SOC_FM_I2S_AWB_PCM@0x11220000 {
			compatible = "mediatek,mt_soc_pcm_fm_i2s_awb";
		};

		MT_SOC_I2S0DL1_PCM@0x11220000 {
			compatible = "mediatek,mt_soc_pcm_dl1_i2s0Dl1";
		};

		MT_SOC_DL1_AWB_PCM@0x11220000 {
			compatible = "mediatek,mt_soc_pcm_dl1_awb";
		};

		MT_SOC_VOICE_MD1_BT@0x11220000 {
			compatible = "mediatek,mt_soc_pcm_voice_md1_bt";
		};

		MT_SOC_VOIP_BT_OUT@0x11220000 {
			compatible = "mediatek,mt_soc_pcm_dl1_bt";
		};

		MT_SOC_VOIP_BT_IN@0x11220000 {
			compatible = "mediatek,mt_soc_pcm_bt_dai";
		};

		MT_SOC_TDMRX_PCM@0x11220000 {
			compatible = "mediatek,mt_soc_tdm_capture";
		};

		MT_SOC_FM_MRGTX_PCM@0x11220000 {
			compatible = "mediatek,mt_soc_pcm_fmtx";
		};

		MT_SOC_UL2_PCM@0x11220000 {
			compatible = "mediatek,mt_soc_pcm_capture2";
		};

		MT_SOC_I2S0_AWB_PCM@0x11220000 {
			compatible = "mediatek,mt_soc_pcm_i2s0_awb";
		};

		MT_SOC_VOICE_MD2@0x11220000 {
			compatible = "mediatek,mt_soc_pcm_voice_md2";
		};

		MT_SOC_ROUTING_PCM@0x11220000 {
			compatible = "mediatek,mt_soc_pcm_routing";
			i2s1clk-gpio = <7 6>;
			i2s1dat-gpio = <5 6>;
			i2s1mclk-gpio = <9 6>;
			i2s1ws-gpio = <6 6>;
		};

		MT_SOC_VOICE_MD2_BT@0x11220000 {
			compatible = "mediatek,mt_soc_pcm_voice_md2_bt";
		};

		MT_SOC_HP_IMPEDANCE_PCM@0x11220000 {
			compatible = "mediatek,Mt_soc_pcm_hp_impedance";
		};

		MT_SOC_CODEC_NAME@0x11220000 {
			compatible = "mediatek,mt_soc_codec_63xx";
		};

		MT_SOC_DUMMY_PCM@0x11220000 {
			compatible = "mediatek,mt_soc_pcm_dummy";
		};

		MT_SOC_CODEC_DUMMY_NAME@0x11220000 {
			compatible = "mediatek,mt_soc_codec_dummy";
		};

		MT_SOC_ROUTING_DAI_NAME@0x11220000 {
			compatible = "mediatek,mt_soc_dai_routing";
		};

		MT_SOC_DAI_NAME@0x11220000 {
			compatible = "mediatek,mt_soc_dai_stub";
		};

		MT_SOC_OFFLOAD_GDMA@0x11220000 {
			compatible = "mediatek,mt_soc_pcm_offload_gdma";
		};

		USB1@0x11260000 {
			compatible = "mediatek,USB1";
			reg = <0x11260000 0x10000>;
		};

		WCN_AHB@0x18000000 {
			compatible = "mediatek,WCN_AHB";
			reg = <0x18000000 0x10000>;
			interrupts = <0 230 0x8>;
		};

		MD_PERIPHERALS@0x20000000 {
			compatible = "mediatek,MD PERIPHERALS";
			reg = <0x20000000 0x0>;
		};

		MD2_PERIPHERALS@0x30000000 {
			compatible = "mediatek,MD2 PERIPHERALS";
			reg = <0x30000000 0x0>;
		};

		C2K_PERIPHERALS@0x38000000 {
			compatible = "mediatek,C2K PERIPHERALS";
			reg = <0x38000000 0x0>;
		};

		G3D_CONFIG@0x13000000 {
			compatible = "mediatek,G3D_CONFIG";
			reg = <0x13000000 0x1000>;
		};

		MALI@0x13040000 {
			compatible = "arm,malit720", "arm,mali-t72x", "arm,malit7xx", "arm,mali-midgard";
			reg = <0x13040000 0x4000>;
			interrupts = <0 214 0x8>, <0 213 0x8>, <0 212 0x8>;
			interrupt-names = "JOB", "MMU", "GPU";
			clock-frequency = <450000000>;
		};

		MMSYS_CONFIG@0x14000000 {
			compatible = "mediatek,MMSYS_CONFIG";
			reg = <0x14000000 0x1000>;
			interrupts = <0 205 0x8>;
		};

		MDP_RDMA@0x14001000 {
			compatible = "mediatek,MDP_RDMA";
			reg = <0x14001000 0x1000>;
			interrupts = <0 187 0x8>;
		};

		MDP_RSZ0@0x14002000 {
			compatible = "mediatek,MDP_RSZ0";
			reg = <0x14002000 0x1000>;
			interrupts = <0 188 0x8>;
		};

		MDP_RSZ1@0x14003000 {
			compatible = "mediatek,MDP_RSZ1";
			reg = <0x14003000 0x1000>;
			interrupts = <0 189 0x8>;
		};

		MDP_WDMA@0x14004000 {
			compatible = "mediatek,MDP_WDMA";
			reg = <0x14004000 0x1000>;
			interrupts = <0 191 0x8>;
		};

		MDP_WROT@0x14005000 {
			compatible = "mediatek,MDP_WROT";
			reg = <0x14005000 0x1000>;
			interrupts = <0 192 0x8>;
		};

		MDP_TDSHP@0x14006000 {
			compatible = "mediatek,MDP_TDSHP";
			reg = <0x14006000 0x1000>;
			interrupts = <0 190 0x8>;
		};

		DISPSYS@0x14007000 {
			compatible = "mediatek,DISPSYS";
			reg = <0x14007000 0x1000>,  /*DISP_OVL0      */
			      <0x14008000 0x1000>,  /*DISP_OVL1      */
			      <0x14009000 0x1000>,  /*DISP_RDMA0     */
			      <0x1400A000 0x1000>,  /*DISP_RDMA1     */
			      <0x1400B000 0x1000>,  /*DISP_WDMA0     */
			      <0x1400C000 0x1000>,  /*DISP_COLOR     */
			      <0x1400D000 0x1000>,  /*DISP_CCORR     */
			      <0x1400E000 0x1000>,  /*DISP_AAL       */
			      <0x1400F000 0x1000>,  /*DISP_GAMMA     */
			      <0x14010000 0x1000>,  /*DISP_DITHER    */
			      <0 0>,  /*DISP_UFOE      */
			      <0x1100E000 0x1000>,  /*DISP_PWM       */
			      <0 0>,  /*DISP_WDMA1     */
			      <0x14015000 0x1000>,  /*DISP_MUTEX     */
			      <0x14013000 0x1000>,  /*DISP_DSI0      */
			      <0x14014000 0x1000>,  /*DISP_DPI0      */
			      <0x14000000 0x1000>,  /*DISP_CONFIG    */
			      <0x14016000 0x1000>,  /*DISP_SMI_LARB0 */
			      <0x14017000 0x1000>,  /*DISP_SMI_COMMOM*/
			      <0x14018000 0x1000>,  /*MIPITX0,real chip would use this:<0x14017000 0x1000>;*/
			      <0x10206000 0x1000>,  /*DISP_CONFIG2*/
			      <0x10210000 0x1000>,  /*DISP_CONFIG3*/
			      <0x10211A70 0x000C>,  /*DISP_DPI_IO_DRIVING1 */
			      <0x10211974 0x000C>,  /*DISP_DPI_IO_DRIVING2 */
			      <0x10211B70 0x000C>,  /*DISP_DPI_IO_DRIVING3 */
			      <0 0>,  /*DISP_DPI_TIMING1 */
			      <0 0>,  /*DISP_DPI_TIMING2 */
			      <0 0>,  /*DISP_DPI_TIMING3 */
			      <0x102100A0 0x1000>,  /*DISP_TVDPLL_CFG6 */
			      <0x10209270 0x1000>,  /*DISP_TVDPLL_CON0 */
			      <0x10209274 0x1000>,  /*DISP_TVDPLL_CON1 */
			      <0x14012000 0x1000>;  /*DISP_OD      */

      interrupts = <0 193 8>, /*DISP_OVL0 */
                   <0 211 8>, /*DISP_OVL1 */
                   <0 194 8>, /*DISP_RDMA0 */
                   <0 195 8>, /*DISP_RDMA1 */
                   <0 196 8>, /*DISP_WDMA0 */
                   <0 197 8>, /*DISP_COLOR */
                   <0 198 8>, /*DISP_CCORR */
                   <0 199 8>, /*DISP_AAL */
                   <0 200 8>, /*DISP_GAMMA */
                   <0 201 8>, /*DISP_DITHER */
                   <0 0 8>, /*DISP_UFOE */
                   <0 117 8>, /*DISP_PWM */
                   <0 0 8>, /*DISP_WDMA1 */
                   <0 186 8>, /*DISP_MUTEX */
                   <0 203 8>, /*DISP_DSI0 */
                   <0 204 8>, /*DISP_DPI0 */
                   <0 205 8>, /*DISP_CONFIG, 0 means no IRQ*/
                   <0 176 8>, /*DISP_SMI_LARB0 */
                   <0 0 8>, /*DISP_SMI_COMMOM*/
                   <0 0 8>,      /*MIPITX0,real chip would use this:<0x14017000 0x1000>;*/
                   <0 0 8>,  /*DISP_CONFIG2*/
                   <0 0 8>,  /*DISP_CONFIG3*/
                   <0 0 8>,  /*DISP_DPI_IO_DRIVING1 */
                   <0 0 8>,  /*DISP_DPI_IO_DRIVING2 */
                   <0 0 8>,  /*DISP_DPI_IO_DRIVING3 */
                   <0 0 8>,  /*DISP_DPI_TIMING1 */
                   <0 0 8>,  /*DISP_DPI_TIMING2 */
                   <0 0 8>,  /*DISP_DPI_TIMING3 */
                   <0 0 8>,  /*DISP_TVDPLL_CFG6 */
                   <0 0 8>,  /*DISP_TVDPLL_CON0 */
                   <0 0 8>,  /*DISP_TVDPLL_CON1 */
                   <0 210 8>;  /*DISP_OD      */
		};

		HDMI@0 {
			compatible = "mediatek,HDMI";
		};

		DPI@0x14014000 {
			compatible = "mediatek,DPI0";
			reg = <0x14014000 0x1000>;
			interrupts = <0 204 0x8>;
		};
                 SMI_LARB0@0x14016000 {
			compatible = "mediatek,SMI_LARB0";
			reg = <0x14016000 0x1000>;
		};

                SMI_COMMON@0x14017000 {
			compatible = "mediatek,SMI_COMMON";
			reg = <0x14017000 0x1000>,  /* SMI_COMMON_EXT */
				<0x14016000 0x1000>,  /* LARB 0 */
				<0x16010000 0x1000>,  /* LARB 1 */
				<0x15001000 0x1000>,  /* LARB 2 */
				<0x17001000 0x1000>;  /* LARB 3 */
		};

		IMGSYS@0x15000000 {
			compatible = "mediatek,IMGSYS";
			reg = <0x15000000 0x1000>;
		};

		SMI_LARB2@0x15001000 {
			compatible = "mediatek,SMI_LARB2";
			reg = <0x15001000 0x1000>;
			interrupts = <0 178 0x8>;
		};

		ISPSYS@0x15000000 {
			compatible = "mediatek,ISPSYS";
			reg = <0x15004000 0x9000>,  /*ISP_ADDR      */
				<0x1500D000 0x1000>,  /*INNER_ISP_ADDR      */
				<0x15000000 0x10000>,  /*IMGSYS_CONFIG_ADDR      */
				<0x10215000 0x3000>,  /*MIPI_ANA_ADDR      */
				<0x10211000 0x1000>;  /*GPIO_ADDR      */

			interrupts = <0 183 0x8>, /* CAM0 */
				<0 184 0x8>, /* CAM1 */
				<0 185 0x8>, /* CAM2 */
				<0 206 0x8>, /* CAMSV0 */
				<0 207 0x8>; /* CAMSV1 */
		};
	  	KD_CAMERA_HW1@0x15008000 {
			compatible = "mediatek,CAMERA_HW";
			reg = <0x15008000 0x1000>;  /* SENINF_ADDR */
		};

		KD_CAMERA_HW2@0x15008000 {
			compatible = "mediatek,CAMERA_HW2";
			reg = <0x15008000 0x1000>;  /* SENINF_ADDR */
		};

		CAM0@0x15004000 {
			compatible = "mediatek,CAM0";
			reg = <0x15004000 0x1000>;
		};

		CAM1@0x15005000 {
			compatible = "mediatek,CAM1";
			reg = <0x15005000 0x1000>;
			interrupts = <0 185 0x8>;
		};

		CAM2@0x15006000 {
			compatible = "mediatek,CAM2";
			reg = <0x15006000 0x1000>;
		};

		CAM3@0x15007000 {
			compatible = "mediatek,CAM3";
			reg = <0x15007000 0x1000>;
		};

		SENINF_TOP@0x15008000 {
			compatible = "mediatek,SENINF_TOP";
			reg = <0x15008000 0x1000>;
			interrupts = <0 182 0x8>;
		};

		CAMSV@0x15009000 {
			compatible = "mediatek,CAMSV";
			reg = <0x15009000 0x1000>;
			interrupts = <0 207 0x8>;
		};

		FDVT@0x1500B000 {
			compatible = "mediatek,FDVT";
			reg = <0x1500B000 0x1000>;
			interrupts = <0 208 0x8>;
		};

		CAM4@0x1500D000 {
			compatible = "mediatek,CAM4";
			reg = <0x1500D000 0x1000>;
		};

		CAM5@0x1500E000 {
			compatible = "mediatek,CAM5";
			reg = <0x1500E000 0x1000>;
		};

		CAM6@0x1500F000 {
			compatible = "mediatek,CAM6";
			reg = <0x1500F000 0x1000>;
		};

		VDEC_GCON@0x16000000 {
			compatible = "mediatek,VDEC_GCON";
			reg = <0x16000000 0x1000>;

		};

		SMI_LARB1@0x16010000 {
			compatible = "mediatek,SMI_LARB1";
			reg = <0x16010000 0x1000>;
			interrupts = <0 177 0x8>;
		};

		VDEC_FULL_TOP@0x16020000 {
			compatible = "mediatek,VDEC_FULL_TOP";
			reg = <0x16020000 0x10000>;
			interrupts = <0 179 0x8>;
		};

		VENC_GCON@0x17000000 {
			compatible = "mediatek,VENC_GCON";
			reg = <0x17000000 0x1000>;
		};

		SMI_LARB3@0x17001000 {
			compatible = "mediatek,SMI_LARB3";
			reg = <0x17001000 0x1000>;
			interrupts = <0 202 0x8>;
		};

		VENC@0x17002000 {
			compatible = "mediatek,VENC";
			reg = <0x17002000 0x1000>;
			interrupts = <0 180 0x8>;
		};

		JPGENC@0x17003000 {
			compatible = "mediatek,JPGENC";
			reg = <0x17003000 0x1000>;
			interrupts = <0 181 0x8>;
		};

		JPGDEC@0x17004000 {
			compatible = "mediatek,JPGDEC";
			reg = <0x17004000 0x1000>;
			interrupts = <0 209 0x8>;
		};

		gpio@0x10000e00 {
			compatible = "mediatek,fpga_gpio";
			reg = <0x10000e00 0x100>;
		};
		CHIPID@08000000 {
			compatible = "mediatek,CHIPID";
			reg = <0x08000000 0x0004>,
                  <0x08000004 0x0004>,
                  <0x08000008 0x0004>,
                  <0x0800000C 0x0004>;
		};
		uibc@0 {
			compatible = "mediatek,uibc";
		};
	};
	psci {
		compatible  = "arm,psci";
		method      = "smc";
		cpu_suspend = <0x84000001>;
		cpu_off     = <0x84000002>;
		cpu_on      = <0x84000003>;
		affinity_info = <0x84000004>;
	};

	MOBICORE {
		compatible = "trustonic,mobicore";
		interrupts = <0 248 0x1>;
	};

/* sensor part */
		hwmsensor@0 {
			compatible = "mediatek,hwmsensor";
		};
		gsensor@0 {
			compatible = "mediatek,gsensor";
		};
		als_ps@0 {
			compatible = "mediatek,als_ps";
		};
		m_acc_pl@0 {
			compatible = "mediatek,m_acc_pl";
		};

		m_alsps_pl@0 {
			compatible = "mediatek,m_alsps_pl";
		};

		m_batch_pl@0 {
			compatible = "mediatek,m_batch_pl";
		};
		batchsensor@0 {
			compatible = "mediatek,batchsensor";
		};
		gyroscope@0 {
			compatible = "mediatek,gyroscope";
		};
		m_gyro_pl@0 {
			compatible = "mediatek,m_gyro_pl";
		};
		barometer@0 {
			compatible = "mediatek,barometer";
	};
		m_baro_pl@0 {
			compatible = "mediatek,m_baro_pl";
		};
		msensor@0 {
			compatible = "mediatek,msensor";
		};
		m_mag_pl@0 {
			compatible = "mediatek,m_mag_pl";
		};
		orientation@0 {
			compatible = "mediatek,orientation";
	};

/* sensor end */

/* early-mount system partition */
	firmware {
		android {
			compatible = "android,firmware";
			fstab {
				compatible = "android,fstab";
				system {
					compatible = "android,system";
					dev = "/dev/block/platform/mtk-msdc.0/11230000.MSDC0/by-name/system";
					type = "ext4";
					mnt_flags = "ro,lazytime,barrier=0";
					fsmgr_flags = "wait";
				};
			};
		};
	};
};

/include/ "cust_eint.dtsi"