xavi/android_kernel_m2note/arch/arm64/crypto/Makefile, branch ng-7.1.2

Revert "GCC: Fix up for gcc 5+"

2018-11-29T23:02:49+00:00

This reverts commit ff505baaf412985af758d5820cd620ed9f1a7e05.

GCC: Fix up for gcc 5+

2018-11-29T11:38:19+00:00

Signed-off-by: mydongistiny Signed-off-by: Mister Oyster

crypto: remove duplicate impl.

2017-12-27T19:17:30+00:00

Revert "crypto: arm64/sha2 - add generated .S files to .gitignore" This reverts commit 9345ccbf273209e3946c3981122d068221a135d2. Revert "crypto: arm64/sha2 - integrate OpenSSL implementations of SHA256/SHA512" This reverts commit 02ea19edc643061fab3b6ea8bd54b96110a9f43b.

backport: crypto: arm64/chacha20 - implement NEON version based on SSE3 code

2017-12-21T14:00:24+00:00

This is a straight port to arm64/NEON of the x86 SSE3 implementation of the ChaCha20 stream cipher. It uses the new skcipher walksize attribute to process the input in strides of 4x the block size. Signed-off-by: Ard Biesheuvel Signed-off-by: Herbert Xu backported to 3.10 the same way arm chacha20 SNEON3 imp. for 3.18 was done : https://android-review.googlesource.com/c/kernel/common/+/551349 Signed-off-by: Mister Oyster

arm64: crypto: increase AES interleave to 4x

2017-12-21T13:35:31+00:00

This patch increases the interleave factor for parallel AES modes to 4x. This improves performance on Cortex-A57 by ~35%. This is due to the 3-cycle latency of AES instructions on the A57's relatively deep pipeline (compared to Cortex-A53 where the AES instruction latency is only 2 cycles). At the same time, disable inline expansion of the core AES functions, as the performance benefit of this feature is negligible. Measured on AMD Seattle (using tcrypt.ko mode=500 sec=1): Baseline (2x interleave, inline expansion) ------------------------------------------ testing speed of async cbc(aes) (cbc-aes-ce) decryption test 4 (128 bit key, 8192 byte blocks): 95545 operations in 1 seconds test 14 (256 bit key, 8192 byte blocks): 68496 operations in 1 seconds This patch (4x interleave, no inline expansion) ----------------------------------------------- testing speed of async cbc(aes) (cbc-aes-ce) decryption test 4 (128 bit key, 8192 byte blocks): 124735 operations in 1 seconds test 14 (256 bit key, 8192 byte blocks): 92328 operations in 1 seconds Signed-off-by: Ard Biesheuvel Signed-off-by: Catalin Marinas (cherry picked from commit 0eee0fbd41c7b57d01136df2519c92ec1506e333) Change-Id: I0fb82b0cc7f685a13c3d15c919be435917e17429

crypto: crc32 - Add ARM64 CRC32 hw accelerated module

2017-12-21T12:26:34+00:00

This module registers a crc32 algorithm and a crc32c algorithm that use the optional CRC32 and CRC32C instructions in ARMv8. Tested on AMD Seattle. Improvement compared to crc32c-generic algorithm: TCRYPT CRC32C speed test shows ~450% speedup. Simple dd write tests to btrfs filesystem show ~30% speedup. Signed-off-by: Yazen Ghannam Acked-by: Steve Capper Acked-by: Ard Biesheuvel Signed-off-by: Herbert Xu

crypto: arm64/sha2 - integrate OpenSSL implementations of SHA256/SHA512

2017-04-16T20:51:50+00:00

This integrates both the accelerated scalar and the NEON implementations of SHA-224/256 as well as SHA-384/512 from the OpenSSL project. Relative performance compared to the respective generic C versions: | SHA256-scalar | SHA256-NEON* | SHA512 | ------------+-----------------+--------------+----------+ Cortex-A53 | 1.63x | 1.63x | 2.34x | Cortex-A57 | 1.43x | 1.59x | 1.95x | Cortex-A73 | 1.26x | 1.56x | ? | The core crypto code was authored by Andy Polyakov of the OpenSSL project, in collaboration with whom the upstream code was adapted so that this module can be built from the same version of sha512-armv8.pl. The version in this patch was taken from OpenSSL commit 32bbb62ea634 ("sha/asm/sha512-armv8.pl: fix big-endian support in __KERNEL__ case.") * The core SHA algorithm is fundamentally sequential, but there is a secondary transformation involved, called the schedule update, which can be performed independently. The NEON version of SHA-224/SHA-256 only implements this part of the algorithm using NEON instructions, the sequential part is always done using scalar instructions. Signed-off-by: Ard Biesheuvel Signed-off-by: Herbert Xu

first commit

2016-08-15T02:19:42+00:00